The present invention relates to integrated circuit packages, and more specifically to a lead frame having terminals that connect an integrated circuit to a printed circuit board with a high degree of compliance to thereby withstand mechanical stress due to thermal changes.
In the mounting of an integrated circuit package on a printed circuit board, or similar such support surface, it is important that the means which physically and electrically interconnect these two structures provide a certain amount of compliance to account for differences in the expansion of the two structures under changing thermal conditions. If sufficient compliance is not provided, the mechanical stress which results when one of the two structures expands or contracts more than the other can lead to a failure of the bond between the two.
The achievement of adequate compliance between the integrated circuit package and the printed circuit board cannot be achieved by merely matching the coefficient of expansion of these two structures. While a perfect thermal expansion coefficient match between the package and the board could assure substantially reliable interconnection when the board and package are subjected to thermal cycling at a relatively low frequency, the bond can nevertheless fail during higher frequency power cycling. Among the factors which can contribute to such failure are the difference in the effective specific heats of the semi-conductor package and the printed circuit board, and the greater thermal radiating area of the board. In other words, because of the greater surface area of the board, it can dissipate heat more rapidly than the semiconductor package and thus may not increase in temperature in the area of the package/board bond as quickly as the package itself, leading to different rates of expansion. This difference in expansion in turn leads to stress in the area of the bond.
This stress must be capable of being absorbed in the bonding media and in the individual elements which make up the total circuit assembly. The most practical means for absorbing this stress is with a compliant interface between the semi-conductor package and the printed circuit board. The degree of compliance which this interface must possess should be such that the elastic limits of the various components and the bonding media are not exceeded under extreme conditions.
Of the presently available types of semiconductor packages, the peripheral leads that can be found on leaded chip carriers and formed lead flat packs provide such compliance to a limited degree. However, these lead arrangements are not suitable for use in array type semiconductor packages, wherein the attachment regions are arranged in a matrix pattern across one surface of the enclosure, rather than merely along the peripheral edges thereof.
Array type packages generally fall into one of three categories: the pin-grid, the pad-grid and the open-via. Of these three types, only the pin-grid arrangement provides any degree of compliance between the semiconductor package and the printed circuit board. However, this design requires a through-hole attachment, with which other limitations are associated. For example, this type of attachment poses alignment problems with respect to the board layers and the bonding pads of the package.
The pad-grid and open-via types of packages utilize a surface attachment rather than a through-hole attachment, which obviates these alignment problems. However, these types of packages, and more specifically the surface mounting arrangement associated with these packages, does not provide the required degree of compliance.